1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method including a CMP (Chemical Mechanical Polishing) process performed for planarizing a surface of a semiconductor substrate.
2. Description of the Related Art
Achievement of a higher and higher integration level in semiconductor devices in these years has been promoting development of a multilayer interconnect structure composed of an increasing number of interconnect layers, to be provided on a semiconductor substrate. Along with such development, a problem of coverage performance of an interconnect layer formed as an upper interconnect layer has become apparent. In order to improve the coverage performance it is necessary to increase planarity of a surface of a semiconductor substrate or a lower interconnect layer, for which purpose a CMP process is popularly utilized, for chemically and mechanically polishing a surface of a semiconductor substrate or a lower interconnect layer with a slurry and a polishing pad. FIGS. 9A to 9D sequentially show a CMP process employed in formation of an isolation insulating film of an STI (shallow trench isolation) structure, including forming a shallow trench on a silicon substrate surface and filling the trench with an insulating material.
Firstly as shown in FIG. 9A, a pad oxide film 102 and a silicon nitride film 103 are formed on a surface of a silicon substrate 101, and a photoresist 104 is formed on the silicon nitride film 103, with an opening at a position corresponding to an isolation region.
Then an etching is performed to selectively remove the silicon nitride film 103 utilizing the photoresist 104 as a mask, after which an etching is again performed to remove a portion of the pad oxide film 102 utilizing the silicon nitride film 103 as a mask, and still an etching is performed on the silicon substrate 101, so as to form a trench (an isolation trench) 105 of a predetermined depth.
Referring to FIG. 9B, after forming a silicon dioxide film (thermally oxidized film) 106 on an inner face of the trench 105, a silicon dioxide film 107 is grown all over the silicon substrate 101 by an HPD-CVD (High-density Plasma CVD (Chemical Vapor Deposition)) process, up to a thickness greater than the depth of the trench 105, so that the trench 105 is filled.
Proceeding to FIG. 9C, a CMP process is performed to polish a surface of the silicon dioxide film 107 on the silicon substrate 101, until the silicon dioxide film 107 remains only inside the trench 105 and right thereabove.
Finally as shown in FIG. 9D, the silicon nitride film 103 is removed by etching, and a wet etching is performed on the surface of the pad oxide film 102 and the silicon dioxide film 107, such that the silicon dioxide film 107 remains only inside the trench 105. At this stage, an STI 110 which serves as an insulating structure for element isolation.
Such technique of planarizing a surface of a semiconductor device having an STI structure by a CMP process is disclosed in JP-A Laid Open No. 2002-252279.
Meanwhile, a silica slurry (SiO) has conventionally been employed in a CMP process to be performed in a case as above. However, in case of employing a silica slurry in a CMP process, such pattern dependence that a polishing rate becomes higher in a smaller area while the polishing rate becomes lower in a larger area is incurred according to the Preston Equation, which makes it difficult to achieve a desired planarity especially in a semiconductor device having a ultrafine pattern. Therefore, employing a ceria slurry (CeO) in a CMP process has recently been proposed, because thereby the problem of the pattern dependence can be minimized.
For example, JP-A Laid Open No. H05-326469 and JP-A Laid Open No. 2001-310256 are proposing to employ a ceria slurry in place of a silica slurry for achieving a higher planarity by a CMP process. A diameter of an abrasive grain of the conventional silica slurry is approximately 0.1 μm, and there is not much difference in the polishing rate between the silicon dioxide film and the silicon nitride film, which is expected to serve as a stopper. Accordingly, the silicon nitride film does not effectively perform as a stopper film, which makes it difficult to achieve a desired CMP effect on a fine pattern. In case of replacing the silica slurry with the ceria slurry described in JP-A Laid Open No. H05-326469 and JP-A Laid Open No. 2001-310256, the polishing rate ratio between the silicon dioxide film and the silicon nitride film may be increased, to thereby reduce the pattern dependence in comparison with the case employing the silica sulurry.
JP-A Laid Open No. 2001-310256 also proposes introducing an additive into the ceria slurry in addition to just employing the ceria slurry, and a surfactant such as a polycarboxylic acid polymer is cited as an example of the additive.
However, it has now been discovered that scratches (scratching during polishing process) are prone to be made on a surface of the silicon dioxide film polished by the abrasive grains during a CMP process since the ceria slurry includes large-diameter abrasive grains. Scratching in an initial stage of the polishing process is not so serious subject since the scratches fade away with the polishing progress. On the other hand, scratches formed shortly before finishing the polishing process remain as it is since there is little portion of the silicon dioxide film left to be polished.
Also, in the CMP process utilizing the ceria slurry, a polishing rate of the silicon dioxide film becomes faster than of the silicon nitride film. Accordingly, the polishing process advances faster especially in a region where the silicon dioxide film occupies a larger area, compared to a region where the silicon dioxide film occupies a smaller area. Therefore the region where the silicon dioxide film is predominant is polished in a recessed shape, thus resulting in a prominent occurrence of a dishing, a phenomenon that adversely the planarity is impaired. A reason that a polishing rate ratio of the silicon dioxide film to the silicon nitride film increases is as follows. While a surface potential of the silicon dioxide film becomes negative when being polished by the ceria slurry, the silicon nitride film tends to have 0 to a positive potential. Therefore the additive bearing a free negative charge in the ceria slurry adsorbs to a surface of the silicon nitride film, to thereby protect a surface of the silicon nitride film from being polished.